These devices are generally used for the active correction of the power factor (PFC) for power supply units with forced switching used in common electronic appliances such as computers, televisions, monitors, etc and to supply fluorescent lamps, in other words pre-regulation stages with forced switching which have the task of absorbing from the network supply a current that is virtually sinusoidal and is in phase with network voltage. Therefore this power supply unit with forced switching therefore comprises a PFC and a DC-DC converter connected to the PFC output.
The traditional power supply unit with forced switching comprises a DC-DC converter and an input stage connected to the electric energy distribution network consisting of a full-wave diode rectifier bridge and of a capacitor connected immediately downstream so as to produce non-regulated direct voltage from the network sinusoidal alternating voltage. The capacitor has sufficiently large capacity for the undulation at its ends to be relatively small compared with a DC level. The bridge rectifier diodes therefore conduct only a small portion of each half cycle of the network voltage because the momentary value of the network voltage is lower than the voltage on the capacitor for most of the cycle. The network current absorbed will accordingly be a series of narrow pulses the amplitude of which is 5 to 10 times the resulting average value.
This has considerable consequences: the current absorbed from the line has peak and effective values that are much greater than in the case of absorption of sinusoidal current, network voltage is distorted by the almost simultaneous pulsed absorption of all the appliances connected to the network, in the case of three-phase systems the current in the neutral conductor is greatly increased and the energy potential of the system for producing electric energy is poorly used. In fact, the wave shape of a pulsed current is very rich in odd harmonic distortions that, whilst not contributing to the power returned to the load, contribute to increasing the effective current absorbed by the network and therefore to increasing the dissipation of energy.
In quantitative terms this can be expressed in terms of power factor (PF), defined as the ratio between real power (the power that the power supply unit returns to the load plus the power dissipated inside it in the form of heat) and apparent power (the product of the effective network voltage and the effective absorbed current), both in terms of total harmonic distortion (THD), generally defined as the percentage ratio between energy associated with all the harmonic distortions of a superior order and that associated with the fundamental harmonic distortion. Typically, a power supply unit with a capacitive filter has a PF between 0.4-0.6 and a THD greater than 100%.
A PFC arranged between the rectifier bridge and the input of the DC-DC converter enables a virtually sinusoidal current to be absorbed from the network, which current is in phase with the voltage and brings PF close to 1 and reduces THD.
The PFCs generally comprise a converter provided with a power transistor and an inductor coupled with it and a control device coupled with the converter in such a way as to obtain from a network alternating input voltage a direct voltage regulated at the output. The control device is capable of determining the period of switch-on time Ton and the period of switch-off time Toff of the power transistor; uniting the period of Ton and the period of Toff time gives the cycle period or switching period of the power transistor.
The commercially available PFC circuit types are basically of two kinds that differ according to the different control technique used: pulse width modulation (PWM) control with fixed frequency wherein current is conducted continuously into an inductor of the power supply unit and variable frequency PWM control, also known as ‘transition mode’ (TM) because the current in the inductor is reset exactly at the end of each switching period. TM control can be operated both by controlling inductor current directly or by controlling the period of Ton time. The fixed-frequency control technique provides better performance but uses complex circuit structure whereas TM technique requires a more simple circuit structure. The first technique is generally used with high power levels whilst the second technique is used with medium to low power levels, normally below 200 W.
FIG. 1 is a diagrammatic view of a PFC pre-regulatory stage of the TM type comprising a boost converter 20 and a control device 1. The boost converter 20 comprises a full-wave diode rectifier bridge 2 with network voltage input Vin, a capacitor C1 (that is used as a high-frequency filter) with a terminal connected to the diode bridge 2 and the other terminal grounded, an inductor L connected to a terminal of the capacitor C1, an MOS power transistor M with the drain terminal connected to an inductance terminal L downstream of the latter, the source terminal being connected to ground (or optionally to ground via a resistance Rs, which is not shown in FIG. 1), a diode D having the anode connected to the common terminal of the inductor L and the transistor M and the cathode connected to a capacitor Co, the other terminal being grounded. The boost converter 20 generates direct output voltage Vout on the capacitor Co that is greater than the network maximum peak voltage, typically 400 V for systems powered by European network supplies or by universal supply. Said output voltage Vout will be the input voltage of the DC-DC converter connected to the PFC.
If it is assumed that the current absorbed from the network by the PFC in virtually stationary running conditions (in other words with constant effective input voltage and constant output load) is sinusoidal in each switch-on cycle of the transistor M, the peak current of the inductor L is Ip=Vin*Ton/L, Ton being the period of time during which the transistor M is switched on. As the input voltage is sinusoidal, if Ton is kept constant during each network cycle, the peak current of the inductor L will be enveloped by a sinusoidal current. An appropriate filter between the network and the input of the rectifier bridge (typically present for questions of electromagnetic compatibility) will filter the input current, eliminating the high-frequency components, so that the current absorbed from the network will be a sinusoidal current of the same frequency and in phase with the network current.
Normally, in PFCs of the TM type controlled in peak-current mode the constancy of switch-on time Ton is a result of forcing the peak current of the inductor to follow a sinusoidal reference. This reference is taken from the rectified voltage after the bridge, the amplitude of which is corrected with the error signal coming from the regulating loop of the output voltage, by means of a multiplier block. The constant Ton approach has the advantage that it does not require reading of the input voltage or of a multiplier block.
The control device 1 maintains the output voltage Vout at a constant value by feedback control. The control device 1 comprises an error amplifier 3 suitable for comparing part of the output voltage Vout, in other words the voltage Vr deriving from Vr=R2*Vout/(R2+R1) (where resistances R1 and R2 are serially connected together and are parallel to the capacitor Co) with a reference voltage Vref, for example 2.5V, and generates an error signal Se proportionate to their difference. The undulation frequency of output voltage Vout is double that of the network voltage and is superimposed on the direct value. However, if the band width of the error amplifier is significantly reduced (typically to below 20 Hz) by means of a compensation capacitor Ccomp and we assume virtually stationary operation, in other words with constant effective input voltage and constant output load, said undulation will be greatly attenuated and the error signal will become constant.
The error signal Se is sent to the inverting input of a comparator PWM 5 whereas at the non-inverting input a ramp signal Sslope persists, which signal is generated by a current generator Ic connected to a VDD supply, a capacitor C and a switch SW When the voltage Sslope equals the voltage Se, the comparator 5 sends a signal to a control block 6 suitable for piloting the transistor M, which in this case switches it off. As the error amplifier output is constant, the duration of the conduction period of the transistor MOS M will be constant within each network cycle. As the network load and/or voltage condition varies the error signal will change and will set the Ton value required to regulate the output voltage. As soon as the transistor MOS is switched off SW is closed and C is unloaded.
After the transistor MOS is switched off the inductor L discharges the energy stored to the load until it is completely emptied. At this point the diode D does not permit the conduction of current and the drain terminal of the transistor M remains floating, so that its voltage Vdrain moves towards the instantaneous input voltage by means of resonance oscillations between the stray capacity of the terminal and the inductance of the inductor L. The drain voltage Vdrain therefore falls rapidly, being coupled by an auxiliary coil of the inductor L with the terminal to which a block 7 is connected that detects current zeroes and that is part of the block 6. This block 7 identifies this negative front, sends a pulsed signal to an OR gate 8, the other input of which is connected to a starter 10 that is suitable for sending a signal to the OR gate 8 at the instant of start time; the output signal S of the gate 8 OR is the set input S of a set-reset flip-flop 11 with another input R that is coupled to receive the output signal of the device 5, it having two output signals, Q and P (P is the negated Q signal). The signal Q is sent to the input of a driver 12, which in this case commands the renewed switch-on of the transistor M (in other cases it can command it to be switched off), and the signal P in this case commands the opening of the switch SW (in other cases it commands it to be closed) in such a way that the capacitor C can recharge, thereby starting a new switching cycle. In this way the PFC works in transition mode.
A PFC absorbs an almost sinusoidal current that is not completely sinusoidal. There are two main sources of the residual distortion, which tends to maintain a significant THD. The first is undulation, the frequency of which is twice that of the network superimposed on the Se signal at the DC level present at the error amplifier output, which introduces a slight modulation of the Ton period of time by producing a 3rd harmonic distortion in the current reference generated by the multiplier. The second is cross distortion, which is seen as a short flat zone in the wave form of the network current IR, at the network voltage zeroes, which correspond to the minimum values VC1 min of the voltage VC1 across the capacitor C1, as shown in FIG. 2, which shows the current IR and the voltage VC1 across the capacitor C1 in two cases with Vin=220 Vac and input power Pin=80 W (FIG. 2a) and Vin=220 Vac and Pin=40 W (FIG. 2b). The cross distortion increases as the PFC load decreases and as effective network voltage increases.
The cause of this distortion is the defective transfer of input-output energy that occurs near the zeroes of the network voltage. In this zone the energy stored in the inductor L is very low, insufficient to load the stray capacity of the drain node of the transistor M to output voltage Vout (typically 400V) so as to enable the passage of current through the diode D and transfer the energy of the inductor L to the output. As a result, the diode is not switched on for a certain number of switching cycles and the energy network remains confined in the resonating circuit consisting of said stray capacity and of the inductor L. This phenomenon, which is accentuated by the presence of the capacitor C1 that filters high frequency, is shown in detail in FIG. 3, wherein the current IR and the voltage Vdrain are shown in a zone wherein the current IR has a substantially flat wave form.